This invention relates to clock synchronization circuits. More particularly, this invention relates to measure-controlled delay (MCD) circuits with reduced phase error. This invention also relates clock synchronization circuits with improved response to process, voltage and temperature (PVT) variations.
Electronic systems often include multiple circuit subsystems (e.g., devices located on a circuit board or chip) that synchronize their respective processes to the same system clock. These processes may be related and required to rigidly comply with precise timing requirements. For example, in high speed memory devices, memory access by one or more electronic circuit subsystems must generally be precisely coordinated. Typically, a clock synchronization circuit synchronizes the clock output by a circuit subsystem to the system clock. This allows the circuit subsystem to perform internal processing and to output the results of this processing according to system timing requirements.
One type of clock synchronization circuit is an MCD circuit. In general, MCD circuits have advantageously faster lock times than do other types of clock synchronization circuits (e.g., digital delay-locked loop (DDLL) circuits). An MCD circuit typically includes a measure delay array, a plurality of sample circuits operative to sample outputs of the measure delay array, and other clock synchronization circuitry. Logic values (i.e., logic “0” or logic “1”) corresponding to samples taken from the outputs of the measure delay array indicate an amount of delay to apply to an input clock in order to generate an output clock. Thus, the output clock is generated with a significant phase error relative to the input clock when the logic values indicate an inappropriate amount of delay. This phase error may adversely affect the ability of an associated circuit subsystem to, for example, comply with system timing requirements.
PVT variations may also adversely affect the ability of a circuit subsystem to comply with system timing requirements. In particular, variations in process, voltage and temperature can prevent a clock synchronization circuit from synchronizing an output clock to an input clock.
In view of the foregoing, it would be desirable to provide measure-controlled delay circuits with reduced phase error. It would also be desirable to provide clock synchronization circuits with improved response to PVT variations.